The invention relates to a semiconductor memory cell and a method for fabricating a semiconductor memory cell.
A semiconductor memory cell can be configured as a DRAM (Dynamic Random Access Memory) cell. The semiconductor memory cell may also be configured as a ferroelectric memory cell. These memory cells include a selection transistor and a capacitor. Depending on the construction, the capacitor is a ferroelectric capacitor with a ferroelectric material or a storage capacitor with a dielectric material. The memory cell is referred to as a stacked memory cell if the selection transistor is formed in a substrate, and the storage capacitor is formed over the selection transistor and the substrate. If a ferroelectric material is utilized for capacitor insulation, for instance if PZT (lead zirconate titanate) or SBT (strontium bismuth tantalate) is used, then a temperature step must be performed in an oxygen atmosphere at over 600xc2x0 C. for longer than a half hour in order to crystallize the ferroelectric material, so that it develops its advantageous ferroelectric characteristics. The disadvantage of exposing the substrate to elevated temperature in an oxygen atmosphere is that conductive regions, for instance silicon or polysilicon regions, are oxidized and thus no longer act as a conductive connection, but rather as an insulator. This can interrupt the electrical connection of the ferroelectric capacitor to the selection transistor.
According to an integration concept of a ferroelectric offset storage cell which is known from the prior art, the lower electrode, which faces the substrate, of the ferroelectric capacitor is fashioned as the common electrode, and the upper electrode of the ferroelectric capacitor forms the respective storage node. This configuration is able to withstand temperature steps at high temperatures in an oxygen atmosphere, because the contact for the electrical connection between the ferroelectric capacitor and the selection transistor is not produced until after the temperature step for recrystallizing the ferroelectric material. As a consequence, an oxidation of this contact owing to the recrystallization is out of the question. The disadvantage of this cell configuration is that the substrate area occupied by this memory cell is larger than 15 F2. F represents the minimum lithographically achievable dimension of the underlying semiconductor technology. This is substantially larger than the 8 F2 which is common today for a DRAM cell. As a consequence, the integration density of this configuration is not particularly large.
According to another configuration of a ferroelectric memory cell taught by the prior art, memory cells of less than 8 F2 are possible. Because the memory node is situated over the selection transistor, this cell configuration is referred to as a stacked cell. Here, the bottom electrode of the storage capacitor is the storage node, and the top electrode can be constructed as a common counterelectrode of all storage capacitors. Alternatively, the counterelectrode can also be structured individually. In this concept, a conductive terminal is required between the bottom electrode and the selection transistor. Because this terminal is usually formed before the ferroelectric capacitor is formed and must therefore endure the temperature step in an oxygen atmosphere, this electrical terminal is normally protected from oxidation at great expense, including additional costs and processing steps. Furthermore, the ferroelectric capacitor must also be protected from the silicon that diffuses out of the electrical contact. The barrier materials that are known from the prior art are presently not able to withstand a temperature step at an elevated temperature, such as would be required for the recrystallization of a ferroelectric material in order to achieve optimal characteristics. Therefore, lower temperatures and shorter time periods are selected for annealing the ferroelectric layer than would be necessary for an optimal ferroelectric character. Furthermore, when recrystallization temperatures are too low, the tendency of SBT is that large leakage currents flow through it. In addition, greater damage can be caused by hydrogen than would be the case given a well crystallized SBT.
U.S. Pat. No. 5,719,416 describes a semiconductor memory cell with a selection transistor and, provided next to this over the semiconductor substrate, a planar storage capacitor. The storage capacitor includes an elongated lower electrode facing in the direction of the transistor. A doped region of the transistor and the elongated portion of the lower electrode of the capacitor are connected to one another. The connecting contact leads through the insulation layer that separates the transistor and the capacitor, and it touches the elongated portion of the capacitor on this top surface, i.e. the surface which is averted from the substrate.
U.S. Pat. No. 5,604,145 teaches a semiconductor memory cell with a capacitor provided over the selection transistor and the semiconductor substrate. A bottom layer of the capacitor is connected to a doped region of the transistor via a vertical contact.
Published European Patent Application No. EP 0 971 392 discloses a memory cell with a selection transistor and a capacitor with a planar layer sequence alongside thereto.
It is accordingly an object of the invention to provide a semiconductor memory cell having a transistor and a capacitor that overcomes the above-mentioned disadvantages of the heretofore-known memory cells of this general type. A further object of the invention is to provide a method for fabricating a semiconductor memory cell.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory cell, including:
a substrate having a surface;
a transistor including a doped region disposed in the substrate;
an insulation layer disposed on the substrate and on the transistor;
an electrically conductive contact extending from the doped region through the insulation layer;
a conductive contact layer disposed on the insulation layer, the conductive contact layer having a first surface facing the surface of the substrate, having a second surface averted from the surface of the substrate, and having a lateral surface connecting the first surface of the conductive contact layer to the second surface of the conductive contact layer;
the electrically conductive contact touching the lateral surface of the conductive contact layer;
a capacitor including a bottom capacitor electrode disposed above the insulation layer, a capacitor insulator disposed on the bottom capacitor electrode, and a top capacitor electrode disposed on the capacitor insulator; and
the electrically conductive contact conductively connecting, via the conductive contact layer, the bottom capacitor electrode to the doped region disposed in the substrate.
In other words, with respect to the semiconductor memory cell, the object of the invention is achieved by a semiconductor memory cell including:
a capacitor, a transistor, a substrate with a surface, and an electrically conductive contact, whereby:
the transistor includes a doped region which is disposed in the substrate;
a first insulation layer is disposed on the substrate and on the transistor;
the electrically conductive contact extends from the doped region through the first insulation layer;
a conductive contact layer is disposed on the first insulation layer; and the conductive contact layer includes a surface facing the surface of the substrate, a surface that is averted from the from the surface of the substrate, and a lateral surface which connects these surfaces;
the capacitor includes a lower capacitor electrode, which is provided over the first insulation layer; a capacitor insulator, which is provided on the lower capacitor electrode; and an upper capacitor electrode, which is provided on the capacitor insulator;
the electrically conductive contact conductively connects the lower capacitor electrode to the doped region via the contact layer; and
the electrically conductive contact touches the lateral surface of the contact layer.
The electrical contact is provided so as to connect the lower capacitor electrode to the doped region. The electrical contact therein is provided alongside the capacitor. This way, a contact hole can be formed in the first insulation layer next to the capacitor without impairing the top capacitor electrode. The bottom capacitor electrode is subsequently electrically connected to the doped region of the transistor through the use of the contact material with which the contact hole is filled.
The contact to the bottom electrode can be self-aligning relative to a conductive layer on which the bottom capacitor electrode is disposed. This layer can include a noble metal or consist of a noble metal. The conductive layer can be buried under the capacitor and protrude alongside the capacitor. The contact hole which is formed beside the capacitor can then partially expose the conductive layer, and a contact material which is filled into the contact hole can conductively connect the conductive layer to the doped region of the transistor. If the conductive layer contains a noble metal, the formation of a non-conductive layer as a result of the thermal recrystallization of the ferroelectric material can be prevented. Another advantage is that the capacitor can be subjected to thermal annealing steps for recrystallization before the electrical contact is formed. This way, temperature steps can even be carried out at temperatures above 800xc2x0 C. and for longer than 45 minutes. With the temperature step, a ferroelectric material acquires optimal characteristics. Another advantage is that the capacitor is completely formed before the electrical contact is formed. In addition, it is possible to forgo an additional diffusion barrier such as would be required for protecting an electrical contact in a recrystallization step at high temperatures. This simplifies the procedure and lowers the costs. Furthermore, it is possible to utilize a substantially thinner bottom electrode than is typically necessary in order to guarantee a diffusion barrier effect for the electrical contact.
Another advantage is that the dielectric or ferroelectric layer is deposited on a planarized wafer surface. The advantage of this is that an increased conformity of the dielectric layer or ferroelectric layer is possible. Another advantage is that the memory node has no additional topology. This is advantageous because the applied dielectric material or ferroelectric material is not stressed by edges or curves at which electrical breakdowns could occur. Another advantage is that the capacitor can be structured with a single masking step. For instance, standard titanium or titanium nitride barriers are suitable for preventing the interaction between the electrical connection and the conductive layer which contains a noble metal and on which the capacitor is formed.
Besides this, what is known as a landed via concept is possible. Here, conductive contacts are formed in a bottom insulating layer as plugs in contact holes. Next, the top insulating layer is applied. According to the invention, a capacitor with a strap is produced in the top dielectric. Contact holes in the top insulating layer are so structured that the surface of the bottom contact plugs in the bottom insulating layer is exposed, so that the contact plugs in the top insulating layer are in conductive contact with the bottom electrode with the bottom contact plugs.
The advantage of the solution according to the invention is that substantially fewer mask exposure steps and thus substantially fewer processing steps are needed, which makes the fabrication process more cost-effective and enables a higher yield.
Furthermore, a memory cell requires only a small portion of the substrate surface, because there is a partial overlap between the bottom capacitor electrode and the conductive layer. As a result, the cell is considerably smaller than an offset cell, in which the top capacitor electrode represents the memory node and is connected to the doped region of the transistor through the use of an electrical contact alongside the capacitor.
For instance, the conductive contact layer can contain platinum or iridium or iridium oxide.
In this application, the term capacitor insulator refers to the insulation between the two electrodes of the capacitor. The capacitor insulator can include a dielectric or ferroelectric material.
An advantageous development of the semiconductor memory cell provides that the electrical contact extend from the doped region through the first insulating layer.
According to another feature of the invention, the electrically conductive contact also touches the conductive contact layer at the second surface averted from the surface of the substrate.
An advantageous development of the invention provides that a conductive contact layer be disposed on the first insulation layer, and that the bottom capacitor electrode be disposed on the conductive contact layer. The conductive contact layer can be slightly out of alignment with respect to the bottom capacitor electrode, i.e. offset relative to it, so that the electrical contact from the doped region through the insulation layer contacts the conductive contact layer but does not touch the capacitor itself.
Another advantageous development of the semiconductor memory cell provides that a second insulation layer be disposed between the first insulation layer and the conductive contact layer. The second insulation layer can act as a diffusion barrier for oxygen and, respectively, for silicon or as an etch stop layer during memory cell fabrication. In a preferred exemplary embodiment, this layer is formed of silicon nitride.
Another advantageous development of the semiconductor memory cell according to the invention provides that a third insulation layer be disposed on the second insulation layer alongside the conductive contact layer. The third insulation layer is disposed alongside the conductive contact layer as a filler material, so that the substrate surface with the embedded conductive contact layer can be planarized by a CMP (Chemical Mechanical Polishing) procedure. The contact layer can be polished (damascene process), but also the third insulation layer, optionally together with the hard mask from the structuring of the contact layer. The advantage of this is that a subsequently deposited dielectric or ferroelectric layer will be deposited on a plane substrate surface and can thus be formed with higher quality.
Another advantageous development of the semiconductor memory cell according to the invention provides that the bottom capacitor electrode include the conductive contact layer. This means that the bottom capacitor electrode is formed somewhat larger than the top capacitor electrode, so that in the formation of the contact hole for the electrical contact, the bottom capacitor electrode is exposed by the contact hole, while the top capacitor electrode remains untouched by the contact hole.
Another advantageous development of the semiconductor memory cell according to the invention provides that the electrical contact touches the conductive layer. This allows an electrical contact between the bottom capacitor electrode and the doped region of the transistor.
Another advantageous development of the semiconductor memory cell according to the invention provides that the conductive contact layer includes a surface on which the bottom capacitor electrode is disposed; the conductive contact layer includes a side wall which is disposed alongside the contact layer; and the electrical contact at least partly touches the surface and the side wall.
This allows a self-aligned electrical contact. In the etching of a contact hole, the conductive contact layer is exposed and acts as an etch mask, whereby a contact, which will subsequently fill the contact hole, touches the conductive layer both laterally and from above.
Another advantageous development of the semiconductor memory cell according to the invention provides that the top capacitor electrode includes a second surface, which is averted from the substrate; and the electrical contact includes a third surface, which is averted from the substrate; and the third surface is further than the second surface from the substrate.
The electrical contact can protrude beyond the capacitor.
With the objects of the invention in view there is also provided, a method of producing a semiconductor memory cell, the method includes the steps of:
providing a substrate;
forming a transistor on the substrate and forming a doped region of the transistor in the substrate;
depositing an insulation layer on the substrate and on the transistor;
forming a structured conductive contact layer with a first surface facing a surface of the substrate, with a second surface averted from the surface of the substrate, and with a lateral surface connecting the first surface and the second surface;
forming a capacitor insulator on the conductive contact layer;
forming a top capacitor electrode on the capacitor insulator;
performing a temperature step for recrystallizing the capacitor insulator;
subsequently forming a contact hole in the insulation layer such that the contact hole is laterally next to the top capacitor electrode and extends to the doped region; and
filling the contact hole with a conductive material such that the conductive contact layer is conductively connected to the conductive material at the lateral surface of the conductive contact layer.
In other words, with respect to the method, the object of the invention is achieved by a method for fabricating a semiconductor memory cell with the steps:
providing a substrate;
forming a transistor on the substrate, thereby forming a doped region of the transistor in the substrate;
depositing a first insulation layer on the substrate and on the transistor;
forming a structured conductive contact layer with one surface facing the surface of the substrate, one surface averted from the surface of the substrate, and a lateral region connecting these surfaces;
forming a capacitor insulator on the conductive contact layer;
forming a top capacitor electrode on the capacitor insulator;
carrying out a temperature step for recrystallizing the capacitor insulator;
next, forming a contact hole alongside the top capacitor electrode in the insulation layer, extending the hole to the doped region;
filling the contact hole with a conductive material, so that the conductive contact layer at the lateral surface is conductively connected to the conductive material.
Another mode of the invention provides that a contact hole be etched into the first insulation layer, exposing the doped region and the conductive contact layer, and that the contact hole is then filled with the electrical contact.
The advantage of forming the electrical contact afterward is that it cannot be affected by a temperature step for recrystallizing the capacitor insulator.
Another advantageous step provides that a bottom electrical contact be formed prior to the deposition of the capacitor insulator in the first insulation layer, and that the electrical contact be formed subsequent to the deposition of the capacitor insulator on the bottom electrical contact, and that it connects the bottom electrical contact to the conductive contact layer.
The electrical contact and the top electrical contact are suitable for realizing what is known as a landed via contact.
An additional advantageous step provides that a bottom capacitor electrode be formed between the conductive contact layer and the capacitor insulator. On one hand, the conductive contact layer can itself be utilized as the bottom capacitor electrode; or on the other hand, a bottom capacitor electrode can be additionally formed on the conductive contact layer, so that an etch selectivity can be achieved, for instance on the basis of the utilized materials. This also makes it possible to lead the contact through under the capacitor.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory cell and method for fabricating a semiconductor memory cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.